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Reconfigurable Computing Lab
The Reconfigurable Computing Lab's research is focused on non-traditional computer system design. This includes (but is not limited to) research into heterogeneous Networks-on-Chip (NoCs), facilitating System-on-Chip (SoC) design through architectural frameworks and CAD tools, using Dynamic Partial Reconfiguration (DPR) to create a flexible architectural framework, on-chip profiling tools that improve runtime performance of Multi-Processor Systems-on-Chip (MPSoCs) and NoCs, trends in FPGA applications, and even quantum computing. The typical application areas for this work are Real-Time and Embedded Systems and we generally use Field Programmable Gate Arrays (FPGAs) to allow us to actually implement and analyze the runtime performance of our designs.
Projects
- Multicore system emulation (PolyBlaze) with OS of abstractions of heterogeneity (FUSE) and run-time system profiling to improve scheduling (ABACUS)
- Reconfigurable Microfluidics.
- Reducing runtime for lengthy computations or complex calculations that need to be resolved in real time.
- Networks-on-Chip on FPGAs.
- Systems Integrating Modules with Predefined Physical Links.
- An architectural framework for Dynamic Parital Reconfiguration.
Contact Us
Email
lshannon@ensc.sfu.ca
Mailing Address:
ASB 8819, 8888 University Drive
Burnaby, B.C. V5A 1S6