Dilshan Kumarathunga
MASc, Heterogeneous Computing Systems Researcher
Discovery II Building
8888 University Dr.
Simon Fraser University
Burnaby, BC V5A 1S6
Email: dilshan_kumarathunga [at] sfu.ca
I am an MASc student at the School of Engineering Science, Simon Fraser University, advised by Prof. Zhenman Fang. My research interests include Computer Architecture, Hardware Accelerators, Reconfigurable Architectures, and Compiler Optimization.
I completed B.Sc. Eng (Hons.) in Electronic & Telecommunication Engineering at the University of Moratuwa, Sri Lanka. My final year undergraduate thesis project, which was done under the supervision of Dr. Ajith Pasqual and Dr. Ranga Rodrigo was accepted and published at ASAP 2019, titled "VLIW Based Runtime Reconfigurable Machine Vision Coprocessor Architecture for Edge Computing". Here, we proposed an FPGA based application specific new architecture for machine vision related operations at the edge nodes.
After that, I had been working as a Senior Applications Engineer at Synopsys Inc., where I was engaged with the FPGA based emulation platform ZeBu, under different aspects like ZeBu front end, power estimation, simulation acceleration flow, and different ZeBu hardware. At Synopsys, I had been able to contribute to different projects involving many EDA tools as well as various HDL constructs and different customer scenarios.
What's New
- September 2022
- Started graduate research at HiAccel Lab
- July 2019
- Presented and published the undergraduate thesis project paper at ASAP 2019
- February 2018
- Started working at Synopsys
- January 2018
- Completed B.Sc. Eng (Hons.) in Electronic & Telecommunication Engineering
- January 2014
- Started B.Sc. Eng (Hons.) in Electronic & Telecommunication Engineering at University of Moratuwa, Sri Lanka
Publications
Conference Papers
| C1 |
VLIW Based Runtime Reconfigurable Machine Vision Coprocessor Architecture for Edge Computing ASAP '19
The widespread use of high definition cameras for surveillance and related tasks has given rise to the concept of edge computing as transmitting and processing video streams in real time have become challenging. However, edge computing at low power and lower cost is difficult with general purpose processor hardware inside cameras. Finding a solution that meets the above requirements and demonstrates flexibility to handle diverse conditions is challenging. In this paper, we propose a coprocessor architecture which is specifically designed to perform machine vision related operations at the edge using very long instruction word (VLIW) architecture. It also supports multiple vision algorithms in the same hardware platform while supporting runtime reconfigurability, architectural flexibility, and extensibility. The system was practically realized on ZedBoard and verified for correct functionality and accuracy at 148.5 MHz. The system is capable of processing 1080p videos at 60 frames per second. Our system performs better than existing reconfigurable architectures and is on par with existing fixed architectures. The architecture can be implemented in the edge nodes of complex vision systems to increase the computational efficiency.
@INPROCEEDINGS{8825133, author={Kumarathunga, Dilshan and Gamage, Omega and Samarasinghe, Asitha and Saranga, Nipuna and Rodrigo, Ranga and Pasqual, Ajith}, booktitle={2019 IEEE 30th International Conference on Application-specific Systems, Architectures and Processors (ASAP)}, title={VLIW Based Runtime Reconfigurable Machine Vision Coprocessor Architecture for Edge Computing}, year={2019}, volume={2160-052X}, number={}, pages={103-106}, doi={10.1109/ASAP.2019.00-22}}
|
Contact
Please contact me via email: dilshan_kumarathunga [at] sfu.ca
Misc
In my free time, I like to read books, listen to music and watch movies.